Current driving capability (i.e., saturation current) and gate-induced drain leakage (GIDL) are two device parameters that can effect the performance of an MOS transistor. Current driving capability is a function of source resistance and the gate oxide thickness and can be improved by providing a thin gate oxide. GIDL, on the other hand, which is caused by band-to-band tunneling in that portion of the gate that overlaps the drain region, is improved by providing a relatively thick gate oxide film where the gate overlaps the drain.
GIDL has made it difficult to provide smaller devices having suitable performance characteristics. In particular, although recent developments in VLSI fabrication techniques have resulted in scaled down device structures having reduced gate oxide thickness, higher GIDL currents, resulting from the reduced gate oxide thickness, have been observed in these device structures.
One technique for reducing GIDL currents involves a symmetrical oxidation process in which a thick gate oxide is provided in regions of gate-source and gate-drain overlap. The thick gate oxide is formed on opposite sides of an etched polysilicon gate electrode (see detailed discussion below) by a polysilicon oxidation process. Although this technique increases the gate oxide thickness adjacent the drain region and therefore reduces GIDL currents, it also increases the thickness of the gate oxide adjacent the source region, which, in turn, increases the source resistance. Driving current, which is related to the source resistance, is therefore reduced.
The above-described symmetrical oxidation process yields improved GIDL currents, but poor driving current characteristics. It has therefore been difficult to provide a scaled down MOS transistor having both suitable GIDL and driving currents characteristics.
A cross-sectional view of a conventional MOS transistor having a symmetrically oxidized structure is shown in FIG. 1. This transistor includes source/drain regions 15 and 16 separated by a channel region 17, each formed in the surface of semiconductor substrate 11. A gate insulation film 12 is formed over channel region 17. Portion 12-1 of the gate insulation film overlying channel region 17, tox1, is less than the thickness of portion 12-2 (formed by polysilicon oxidation) overlying source and drain region 15 and 16, tox2. As further shown in FIG. 1, a gate electrode 13 is formed on gate insulation film 12.
A process for fabricating the transistor shown in FIG. 1 will now be described with reference to FIGS. 2(a) to 2(c).
As shown in FIG. 2(a), oxide film 12-1 is grown on a p-type semiconductor substrate 11 by thermal oxidation. A polysilicon film is then deposited on oxide film 12-1. The polysilicon film is then patterned by a photoetching process to form gate electrode 13, leaving exposed portions of oxide 12-1.
As seen in FIG. 2(b), a polysilicon oxidation process is then performed at a relatively low temperature (850.degree.-900.degree. C.), the exposed oxide films on both sides of the gate are oxidized to form thicker oxide films 12-2.
Referring to FIG. 2(c), n+type source/drain regions 15 and 16 are formed in the substrate beneath the thicker oxide films 122 by ion implantation of n-type impurity ions 14. During this step, gate 13 is used as an implantation mask. Accordingly, a gate insulation film 12 having portion 12-1 with a thickness tox1 is formed beneath gate 13 and oxide films 12-2 having a thickness tox2 is formed over source and drain regions 15 and 16, the thickness tox1 being less than the thickness tox2. In addition, the device formed by the above-described polysilicon oxidation process is symmetrical in that thick oxide films are formed on both sides of gate 13.
As noted above, this process yields an MOS transistor device having reduced GIDL current (due to thicker oxide 12-2 over the drain region than thin oxide 12-1) but poor driving current characteristics (due to the same thick oxide 12-2 over the source region creating a high source resistance).
FIG. 3 illustrates a different type of symmetrical transistor which is used in a flash-EEPROM. This transistor is formed on a p-type substrate 21 and includes a channel region 29 formed between n+ source/drain regions 27 and 28, respectively. A gate insulation film is formed so as to overly both source and drain regions 27 and 28, as well as channel region 29. The portion of the gate insulation film overlying source and drain regions 27 and 28, oxide film 22-2, has a thickness tox4. The thickness of gate insulation film portion 22-1 above channel region 29, tox3, is less than tox4.
The symmetrical flash-EEPROM transistor shown in FIG. 3 further includes a charge storing floating gate 23 formed on the portion of the gate insulation film overlying the channel region. An interlayer insulation film 24 is sandwiched between floating gate 23 and control gate 25.
The transistor shown in FIG. 3 is termed "symmetrical" because thick oxide films 22-2 are provided over both the source and drain regions of the device.
The processing steps for forming the flash-EEPROM transistor shown in FIG. 3 include first growing an oxide film 22-1 on substrate 21 by thermal oxidation. A first polysilicon film is then deposited on oxide film 22-1, and then interlayer insulation and second polysilicon films are successively formed on the first polysilicon film. The first polysilicon film, interlayer film and the second polysilicon film are then patterned by a photoetching process. As a result, floating gate 23, interlayer insulation film 24 and control gate 25 are formed. A polysilicon oxidation process is then performed to produce thick oxide film portions 222 (i.e., thicker than oxide film portion 22-1) on opposite sides of the floating and control gates. N+ source and drain regions 27 and 28, respectively are formed by ion implantation of n-type impurities into the substrate using the control gate as an implantation mask.
Programming and erasing information in the flash-EEPROM transistor will now be described. During programming, a relatively high voltage is applied to control gate 25, causing a strong electric field to be formed beneath the control gate. This electric field creates hot electrons in a conductive region of channel region 29, which are induced onto the floating electrode 23 through oxide film 22-1. These electrons remain on the floating electrode and represent a bit of information to be stored in the flash-EEPROM. Information is erased by applying a relatively low voltage, causing electrons on the floating gate 23 to return to the channel region through oxide film 22-1.
The flash-EEPROM transistor shown in FIG. 3 suffers from disadvantages similar to those discussed above with respect to the transistor illustrated in FIG. 1. Namely, although GIDL currents are reduced because of the symmetrically formed thick oxide film, the device has low driving current characteristics because of the increased source resistance due to this thick oxide film overlying the source region.